One of the goals in the fabrication of electronic components is to minimize the size of various components. For example, it is desirable that handheld devices such as cellular telephones and personal digital assistants (PDAs) be as small as possible. To achieve this goal, the semiconductor circuits that are included within the devices should be as small as possible. One way of making these circuits smaller is to stack the chips that carry the circuits.
A number of ways of interconnecting the chips within the stack are known. For example, bond pads formed at the surface of each chip can be wire-bonded, either to a common substrate or to other chips in the stack. Another example is a so-called micro-bump 3D package, where each chip includes a number of micro-bumps that are routed to a circuit board, e.g., along an outer edge of the chip. However, introduction of such interconnects may introduce additional challenges.
The integration of chips brings-forth a number of new challenges that need to be addressed. One of the challenges arises due to heating required to form an adhesive bond between the two chips or between a chip and a substrate. Problems due to heating include wafer bowing as well melting of critical components within the chips. These challenges increase dramatically as the diameter of the wafer increases. Hence, what is needed in the art are improved structures and methods of producing structures for chip bonding that overcome these and other challenges.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.